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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\MiniLED_driver.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\SPI7001_pack\SPI7001_gowin.vp<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\led_part\led_pll\7001_rpll.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\lvds_7to1_rx\LVDS71RX_1CLK8DATA.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\lvds_7to1_rx\bit_align_ctl.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\lvds_7to1_rx\gowin_rpll\LVDS_RX_rPLL.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\lvds_7to1_rx\lvds_7to1_rx_defines.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\lvds_7to1_rx\lvds_7to1_rx_top.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\lvds_7to1_rx\word_align_ctl.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\lvds_7to1_tx\gowin_rpll\LVDS_TX_rPLL.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\lvds_7to1_tx\ip_gddr71tx.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\lvds_7to1_tx\lvds_7to1_tx_defines.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\lvds_7to1_tx\lvds_7to1_tx_top.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\lvds_video_top.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\ramflag_1.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\sdpb360\sdpb360.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\sram_top_pack\sram_top_gowin.vp<br>
C:\Gowin\Gowin_V1.9.10.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v<br>
C:\Gowin\Gowin_V1.9.10.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v<br>
C:\Gowin\Gowin_V1.9.10.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v<br>
C:\Gowin\Gowin_V1.9.10.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v<br>
C:\Gowin\Gowin_V1.9.10.02_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v<br>
C:\Gowin\Gowin_V1.9.10.02_x64\IDE\data\ipcores\gw_jtag.v<br>
C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.10.02</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV55PG484C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-55</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sat Nov  9 01:37:58 2024
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>lvds_video_top</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.57s, Peak memory usage = 771.410MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.116s, Peak memory usage = 771.410MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 771.410MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.1s, Peak memory usage = 771.410MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 771.410MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 771.410MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 771.410MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 771.410MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 771.410MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 771.410MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 771.410MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 771.410MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.106s, Peak memory usage = 771.410MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.169s, Peak memory usage = 771.410MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 771.410MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>41</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>31</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>6</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>15</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspTLVDS_IBUF</td>
<td>5</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspTLVDS_OBUF</td>
<td>5</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>1417</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>169</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFE</td>
<td>254</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFS</td>
<td>16</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>19</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>20</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFP</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>33</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>344</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>554</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>1586</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>202</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>377</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>1007</td>
</tr>
<tr>
<td class="label"><b>MUX </b></td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspMUX16</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>75</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>75</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>31</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>31</td>
</tr>
<tr>
<td class="label"><b>IOLOGIC </b></td>
<td>14</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIVIDEO</td>
<td>5</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOVIDEO</td>
<td>5</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIODELAY</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>DSP </b></td>
<td></td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspMULTADDALU18X18</td>
<td>2</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>17</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>16</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbsppROM</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>CLOCK </b></td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspCLKDIV</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbsprPLL</td>
<td>3</td>
</tr>
<tr>
<td class="label"><b>Black Box </b></td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspGW_JTAG</td>
<td>1</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>1700(1625 LUT, 75 ALU) / 54720</td>
<td>4%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>1417 / 41997</td>
<td>4%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 41997</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>1417 / 41997</td>
<td>4%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>17 / 140</td>
<td>13%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>1</td>
<td>I_clkin_p</td>
<td>Base</td>
<td>11.976</td>
<td>83.5</td>
<td>0.000</td>
<td>5.988</td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I </td>
</tr>
<tr>
<td>2</td>
<td>I_clk</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>I_clk_ibuf/I </td>
</tr>
<tr>
<td>3</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>3.422</td>
<td>292.2</td>
<td>0.000</td>
<td>1.711</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>4</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>3.422</td>
<td>292.2</td>
<td>0.000</td>
<td>1.711</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>5</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>6.843</td>
<td>146.1</td>
<td>0.000</td>
<td>3.422</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>6</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>10.265</td>
<td>97.4</td>
<td>0.000</td>
<td>5.133</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>7</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>40.000</td>
<td>25.0</td>
<td>0.000</td>
<td>20.000</td>
<td>I_clk_ibuf/I</td>
<td>I_clk</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>8</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>40.000</td>
<td>25.0</td>
<td>0.000</td>
<td>20.000</td>
<td>I_clk_ibuf/I</td>
<td>I_clk</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>9</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>1040.000</td>
<td>1.0</td>
<td>0.000</td>
<td>520.000</td>
<td>I_clk_ibuf/I</td>
<td>I_clk</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>10</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>120.000</td>
<td>8.3</td>
<td>0.000</td>
<td>60.000</td>
<td>I_clk_ibuf/I</td>
<td>I_clk</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>11</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>11.976</td>
<td>83.5</td>
<td>0.000</td>
<td>5.988</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT </td>
</tr>
<tr>
<td>12</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>3.422</td>
<td>292.2</td>
<td>0.000</td>
<td>1.711</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>13</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>3.422</td>
<td>292.2</td>
<td>0.000</td>
<td>1.711</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>14</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>6.843</td>
<td>146.1</td>
<td>0.000</td>
<td>3.422</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>15</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>10.265</td>
<td>97.4</td>
<td>0.000</td>
<td>5.133</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTD3 </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>I_clkin_p</td>
<td>83.500(MHz)</td>
<td>363.927(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>I_clk</td>
<td>50.000(MHz)</td>
<td>172.891(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk</td>
<td>25.000(MHz)</td>
<td>87.504(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>4</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>0.962(MHz)</td>
<td>261.233(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
<tr>
<td>5</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
<td>83.500(MHz)</td>
<td>170.068(MHz)</td>
<td>7</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.126</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>13.383</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.509</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.317</td>
<td>0.341</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>12.677</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/CLK</td>
</tr>
<tr>
<td>12.909</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/Q</td>
</tr>
<tr>
<td>13.383</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0/CALIB</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>13.687</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk</td>
</tr>
<tr>
<td>14.184</td>
<td>0.497</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP</td>
</tr>
<tr>
<td>14.544</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0/FCLK</td>
</tr>
<tr>
<td>14.509</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0</td>
</tr>
<tr>
<td>14.509</td>
<td>0.000</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.156</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>1.711</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.474, 67.139%; tC2Q: 0.232, 32.861%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.126</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>13.383</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.509</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.317</td>
<td>0.341</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>12.677</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/CLK</td>
</tr>
<tr>
<td>12.909</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/Q</td>
</tr>
<tr>
<td>13.383</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1/CALIB</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>13.687</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk</td>
</tr>
<tr>
<td>14.184</td>
<td>0.497</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP</td>
</tr>
<tr>
<td>14.544</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1/FCLK</td>
</tr>
<tr>
<td>14.509</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1</td>
</tr>
<tr>
<td>14.509</td>
<td>0.000</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.156</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>1.711</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.474, 67.139%; tC2Q: 0.232, 32.861%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.126</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>13.383</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.509</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.317</td>
<td>0.341</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>12.677</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/CLK</td>
</tr>
<tr>
<td>12.909</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/Q</td>
</tr>
<tr>
<td>13.383</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2/CALIB</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>13.687</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk</td>
</tr>
<tr>
<td>14.184</td>
<td>0.497</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP</td>
</tr>
<tr>
<td>14.544</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2/FCLK</td>
</tr>
<tr>
<td>14.509</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2</td>
</tr>
<tr>
<td>14.509</td>
<td>0.000</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.156</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>1.711</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.474, 67.139%; tC2Q: 0.232, 32.861%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.126</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>13.383</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.509</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.317</td>
<td>0.341</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>12.677</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/CLK</td>
</tr>
<tr>
<td>12.909</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/Q</td>
</tr>
<tr>
<td>13.383</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3/CALIB</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>13.687</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk</td>
</tr>
<tr>
<td>14.184</td>
<td>0.497</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP</td>
</tr>
<tr>
<td>14.544</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3/FCLK</td>
</tr>
<tr>
<td>14.509</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3</td>
</tr>
<tr>
<td>14.509</td>
<td>0.000</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.156</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>1.711</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.474, 67.139%; tC2Q: 0.232, 32.861%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.126</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>13.383</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.509</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.317</td>
<td>0.341</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>12.677</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/CLK</td>
</tr>
<tr>
<td>12.909</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/Q</td>
</tr>
<tr>
<td>13.383</td>
<td>0.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A/CALIB</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>13.687</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk</td>
</tr>
<tr>
<td>14.184</td>
<td>0.497</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP</td>
</tr>
<tr>
<td>14.544</td>
<td>0.360</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A/FCLK</td>
</tr>
<tr>
<td>14.509</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A</td>
</tr>
<tr>
<td>14.509</td>
<td>0.000</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.156</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>1.711</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.474, 67.139%; tC2Q: 0.232, 32.861%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.360, 100.000%</td></tr>
</table>
<br/>
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